 Wide operating voltage range: (@ 4 CPU clock per instruction, i.e. 4T mode)

∙ 2.4V ~ 5.5V @system clock ≦8MHz.

 Wide operating temperature: -40°C ~ 85°C.

 1K x 14 bits MTP.

 64 bytes SRAM.

 64 bytes EEPROM.

 6 general purpose I/O pins (GPIO), PB[5:0], with independent direction control.

 PB[3:0] have features of Pull-Low resistor for input pin.

 PB[5:0] have features of Pull-High resistor, and open-drain output.

 8-level hardware Stack.

 Direct and indirect addressing modes for data access.

 One 8-bit up-count timer (Timer0) with programmable prescaler.

 One 10-bit reload or continuous down-count timers (Timer1).

 Three 10-bit resolution PWM (PWM1/2/3) output.

 One buzzer (BZ1) output.

 Selectable 38/57KHz IR carrier frequency and high/low polarity according to data value.

 Built-in Power-On Reset (POR).

 Built-in high-precision Low-voltage detector(LVD) .

 Built-in Low-Voltage Reset (LVR).

 Built-in 16-segment Low-Voltage Detect (LVD).

 Built-in Watch-Dog Timer (WDT) enabled/disabled by firmware control.

 Dual-clock oscillation: System clock can switch between high oscillation and low oscillation.

∙ High oscillation: I_HRC (Internal High Resistor/Capacitor Oscillator ranging from 1M~20MHz)

∙ Low oscillation: I_LRC (Internal 32KHz oscillator)

 Four kinds of operation mode to reduce system power consumption:

∙ Normal mode, Slow mode, Standby mode and Halt mode.

 Seven hardware interrupt events:

∙ Timer0 overflow interrupt.

∙ Timer1 underflow interrupt.

∙ WDT timeout interrupt.

∙ PB input change interrupt.

∙ External interrupt.

∙ LVD interrupt.

∙ End of EEPROM write interrupt.

 Six interrupt events to wake-up from Standby mode:

∙ Timer0 overflow interrupt.

∙ Timer1 underflow interrupt.

∙ WDT timeout interrupt.

∙ PB input change interrupt.

∙ External interrupt.

∙ LVD interrupt.

 Three interrupt events to wake-up from Halt mode.

∙ WDT timeout interrupt.

∙ PB input change interrupt.

∙ External interrupt.

 There are two current options (Small / Normal )can be selected.